This U.S. nonprovisional patent application claims priority under 35 U.S.C. § 119 of Korean Patent Application 2002-45913 filed on Aug. 2, 2002, the entire contents of which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having consistent skew over the entire memory core thereof.
2. Description of Related Art
Semiconductor memory has become a mainstay of digital electronic devices. Increasing the operating speed of semiconductor memory remains an on-going pursuit for research in the semiconductor field. For example, processor speeds in a typical personal computer have crossed the gigahertz threshold, and hence require high speed memory and bus architectures to achieve higher throughput. Improving the design of memory devices provides a significant opportunity in increasing memory operating speeds.
Memory designers aspire to overcome skew of the memory core to increase the access and read-write speed of a memory device. The presence of skew reduces the operating speed of the memory device. Further, the presence of asymmetric or inconsistent skew over a memory core poses a hurdle in increasing the operating speed of a semiconductor memory device.
Further, the operating speed of the semiconductor memory increases when there is a decrease in signal margin. The presence of skew, for example, inconsistent skew, inhibits reduction of signal margin, and consequently the increase of memory speeds.
FIG. 1 illustrates a schematic diagram of a memory core of a conventional semiconductor memory device. As shown in FIG. 1, a conventional semiconductor memory device includes a memory core 10 and a data input/output circuit 20 positioned below the memory core 10. As an example, the memory core 10 is divided into four sections including a first section A positioned at left upper corner, a second section B positioned at right upper corner, a third section C positioned at left lower corner and a fourth section D positioned at right lower corner. The time for transferring a signal or data from the first section A to the second section B, or vice versa is denoted by tAB. Further, the time for transferring a signal or data from the second section B to the fourth section D, or vice versa is denoted by tBD. A row control signal Sro starts from the right side of the data input/output circuit 20 and proceeds upward along the right side of the memory core 10. In the memory core 10, the row control signal Sro horizontally runs from right to left. On the other hand, a column control signal Sco starts from the center PC of the data input/output circuit 20, proceeds to the both sides of the data input/output circuit 20 in a horizontal direction. In the memory core 10, the column control signal Sco vertically runs from down to up.
The total data outputting time required for outputting data from each of the sections A-D of the memory core is calculated as follows. For the first section A, the total data outputting time Tdout for outputting data from the first section A of the memory core 10 is equal to the sum of a time tBD+tAB required for the row control signal Sro to reach the first section A, a time tAB/2+tBD required for the column control signal Sco to reach the first section A, a time tRA which is an operating time of the memory core in the first section A and a time tBD required for data to run from an input/output line 10 to the data input/output circuit 20; that is, Tdout=(3/2)tAB+3tBD+tRA.
For the second section B, the total data outputting time Tdout for outputting data from the second section B of the memory core is equal to the sum of a time tBD required for the row control signal to reach the second section B, a time tAB/2+tBD required for the row control signal to reach the second section B, a time tRB which is an operating time of the memory core at the second section B and a time tBD required for data to run from an input/output line 10 to the data input/output circuit 20; that is, Tdout=(1/2)tAB+3tBD+tRB.
For the third section C, the total data outputting time Tdout for outputting data from the third section C of the memory core is equal to the sum of a time tAB required for the row control signal to reach the third section C, a time tAB/2 required for the column control signal to reach the second section B of the memory core, a time tRC which is an operating time of the memory core at the third section C and a time “0” required for data to run from an input/output line 10 to the data input/output circuit 20; that is, Tdout=(3/2)tAB+tRC.
For the fourth section D, the total data outputting time Tdout for outputting data from the fourth section D of the memory core is equal to the sum of a time “0” required for the row control signal to reach the fourth section D, a time tAB/2 required for the column control signal to reach the fourth section D of the memory core, and a time tRD which is an operating time of the memory core at the fourth section D and a time “0” required for data to run from an input/output line 10 to the data input/output circuit 20; that is, Tdout=(1/2)tAB+tRD.
The time for the row control signal Sro to reach the first section A is tAB+tBD, and the time for the row control signal Sro to reach the fourth sections D is “0”. Accordingly, signal skew is caused between the first section A and the fourth section D by the time tAB+tBD. A column control operation must begin after a row control operation is ended in the first section A to which the row control signal is reached last. Accordingly, undesired time loss of tAB+tBD occurs for the fourth section D. Further, the time for the column control signal Sco to reach the fourth section D is (1/2)tAB, and the time for the column control signal Sco to reach the first section A is (1/2)tAB+tBD. Accordingly, the column control signal is skewed between the first section A and the fourth section D by the time tBD. Still further, the time required for data to run from an independent input/output line 10 to the data input/output circuit 20 is “0” for the fourth section D and tBD for the first section A.
If the operating times of the memory core at the first to fourth sections A-D are the same, tRA=tRB=tRC=tRD. Then, a difference between the total data outputting times Tdout in the first section A and the fourth section D is tAB+3tBD. Accordingly, in the conventional semiconductor memory device, the signal skew is caused by the time tAB+3tBD between the best corner and the worst corner.
In the conventional semiconductor device as described above, signal margin reduction is limited because of the signal skew, and therefore it is difficult to improve an operating speed of the semiconductor memory device.